Nasdaq

Semidynamics and Arteris Partner To Accelerate AI RISC-V System-on-Chip Development

Arteris and Semidynamics partnership enhances the flexibility and highly configurable interoperability of RISC-V processor IP with system IP. Integrated and optimized solutions will focus on ...
EE World Online

What are the benefits of RISC-V in AI, ML, and embedded systems?

The open-source nature of RISC-V brings the benefits of a modular and royalty-free instruction set architecture (ISA) that eliminates licensing fees, can accelerate development, and fosters ...
Geeky Gadgets

RISC OS alternative operating system hits Kickstarter

A new Kickstarter project has launched this month, looking for backers to help build a power saving computer operating system and push RISC OS to more hardware platforms. German developer Stefan ...
Business Insider

Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification

SAN JOSE, Calif., Feb. 20, 2025 (GLOBE NEWSWIRE) -- Breker Verification Systems today confirmed its RISC-V SystemVIP library components and test suite synthesis product portfolio is deployed in more ...
EDN

Breker Verification Systems Launches Unique RISC-V TrekApp for Automated, High-Coverage System Integration Test Suite Synthesis

Developed with SiFive to address RISC-V system integration validation; generates high-impact SoC verification test suite with minimal manual effort. Breker Verification Systems, the leading provider ...
TechNode

China’s chip industry is embracing RISC-V

Every Wednesday and Friday, TechNode’s Briefing newsletter delivers a roundup of the most important news in China tech, straight to your inbox. Sign up On June 21, Nuclei System Technology, a Shanghai ...
TweakTown

RISC-V systems support replacing RAM sticks WITHOUT powering off the system

The upcoming version 6.11 of the mainline Linux kernel has support for RISC-V memory hot plugging, meaning you can pull RAM sticks out of your PC without turning it off... very nice. The Linux kernel ...
The Next Platform

Strong Showing for First Experimental RISC-V Supercomputer

A European team of university students has cobbled together the first RISC-V supercomputer capable of showing balanced power consumption and performance. More importantly, it demonstrates a potential ...
Design And Reuse

RISC-V IP Core Portfolio at Embedded World 2026, Powering Next-Gen Embedded Systems for Automotive, IoT & Industrial Systems…

T2M will be participating in Embedded World 2026, from March 10 to 12, 2026, in Nuremberg, Germany, to showcase its full range of production-proven RISC-V CPU IP cores. Extracted from silicon and ...
Semiconductor Engineering

Tag-Based Memory Verification System for RISC-V (Inha Univ., Intel Labs et al.)

A new technical paper titled “Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems” was published by researchers at Inha University, Intel Labs, Electronics and ...
Ars Technica

A history of ARM, part 1: Building the first chip

RISC is a somewhat misleading term, as a RISC processor doesn't *have* to have fewer instructions in its ISA than a CISC system (Though RISC architectures do tend to try to do so). For example, the ...