Semiconductor Engineering

Cell Library Verification Using Symbolic Simulation

Standard cell libraries have been a mainstay of chip design for many decades since the inception of logic synthesis and composition methodologies. Cell library IP typically contains Verilog models ...
Business Wire

SilTerra Leverages Silvaco's Library Characterization and Optimization Tools to Boost Efficiency in the Development of its Foundry Standard Cell IPs

SANTA CLARA, Calif.--(BUSINESS WIRE)--Silvaco Group, Inc. (“Silvaco”), a provider of TCAD, EDA software, and design IP, today announced that SilTerra has successfully deployed its library ...
Semiconductor Engineering

Transformer Model Based Clustering Methodology For Standard Cell Layout Automation (Nvidia)

A new technical paper titled “Novel Transformer Model Based Clustering Method for Standard Cell Design Automation” was published by researchers at Nvidia. “Standard cells are essential components of ...
Electronic Design

Understanding Cell-Aware ATPG And User-Defined Fault Models

ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.